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| MC34152, MC33152, NCV33152 High Speed Dual MOSFET Drivers The MC34152/MC33152 are dual noninverting high speed drivers specifically designed for applications that require low current digital signals to drive large capacitive loads with high slew rates. These devices feature low input current making them CMOS/LSTTL logic compatible, input hysteresis for fast output switching that is independent of input transition time, and two high current totem pole outputs ideally suited for driving power MOSFETs. Also included is an undervoltage lockout with hysteresis to prevent system erratic operation at low supply voltages. Typical applications include switching power supplies, dc-to-dc converters, capacitor charge pump voltage doublers/inverters, and motor controllers. This device is available in dual-in-line and surface mount packages. Features http://onsemi.com MARKING DIAGRAMS 8 PDIP-8 P SUFFIX CASE 626 1 1 8 8 1 SOIC-8 D SUFFIX CASE 751 1 x A WL, L YY, Y WW, W = 3 or 4 = Assembly Location = Wafer Lot = Year = Work Week 3x152 ALYW MC3x152P AWL YYWW 8 * * * * * * * * * Pb-Free Packages are Available Two Independent Channels with 1.5 A Totem Pole Outputs Output Rise and Fall Times of 15 ns with 1000 pF Load CMOS/LSTTL Compatible Inputs with Hysteresis Undervoltage Lockout with Hysteresis Low Standby Current Efficient High Frequency Operation Enhanced System Performance with Common Switching Regulator Control ICs NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes VCC 6 + - 5.7V Drive Output A Logic Input A 2 7 100k PIN CONNECTIONS N.C. 1 Logic Input A 2 GND 3 Logic Input B 4 (Top View) 8 N.C. 7 Drive Output A 6 VCC 5 Drive Output B ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Drive Output B Logic Input B 4 5 100k GND 3 Figure 1. Representative Diagram (c) Semiconductor Components Industries, LLC, 2004 1 October, 2004 - Rev. 7 Publication Order Number: MC34152/D MC34152, MC33152, NCV33152 MAXIMUM RATINGS Rating Power Supply Voltage Logic Inputs (Note 1) Drive Outputs (Note 2) Totem Pole Sink or Source Current Diode Clamp Current (Drive Output to VCC) Power Dissipation and Thermal Characteristics D Suffix, Plastic Package Case 751 Maximum Power Dissipation @ TA = 50C Thermal Resistance, Junction-to-Air P Suffix, Plastic Package, Case 626 Maximum Power Dissipation @ TA = 50C Thermal Resistance, Junction-to-Air Operating Junction Temperature Operating Ambient Temperature Operating Ambient Temperature Operating Ambient Temperature Storage Temperature Range Electrostatic Discharge Sensitivity (ESD) Human Body Model (HBM) Machine Model (MM) MC34152 MC33152 MC33152V NCV33152 , Symbol VCC Vin IO IO(clamp) Value 20 -0.3 to +VCC 1.5 1.0 Unit V V A PD RqJA PD RqJA TJ TA 0.56 180 1.0 100 +150 0 to +70 -40 to +85 -40 to +125 -65 to +150 2000 200 W C/W W C/W C C Tstg ESD C V Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. For optimum switching speed, the maximum input voltage should be limited to 10 V or VCC, whichever is less. 2. Maximum package power dissipation limits must be observed. ORDERING INFORMATION Device MC34152D MC34152DG MC34152DR2 MC34152DR2G MC34152P MC33152D MC33152DR2 MC33152P MC33152PG MC33152VDR2 NCV33152DR2* NCV33152DR2G* Package SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) PDIP-8 SOIC-8 SOIC-8 PDIP-8 PDIP-8 (Pb-Free) SOIC-8 SOIC-8 SOIC-8 (Pb-Free) Shipping 98 Units / Rail 98 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 50 Units / Rail 98 Units / Rail 2500 Tape & Reel 50 Units / Rail 50 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV prefix is for automotive and other applications requiring site and change control. http://onsemi.com 2 MC34152, MC33152, NCV33152 ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = 25C, for min/max values TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.) Characteristics LOGIC INPUTS Input Threshold Voltage Output Transition High-to-Low State Output Transition Low-to-High State Input Current High State (VIH = 2.6 V) Low State (VIL = 0.8 V) DRIVE OUTPUT Output Voltage Low State (Isink = 10 mA) Low State (Isink = 50 mA) Low State (Isink = 400 mA) High State (Isource = 10 mA) High State (Isource = 50 mA) High State (Isource = 400 mA) Output Pull-Down Resistor SWITCHING CHARACTERISTICS (TA = 25C) Propagation Delay (CL = 1.0 nF) Logic Input to: Drive Output Rise (10% Input to 10% Output) Drive Output Fall (90% Input to 90% Output) Drive Output Rise Time (10% to 90%) Drive Output Rise Time (10% to 90%) Drive Output Fall Time (90% to 10%) Drive Output Fall Time (90% to 10%) TOTAL DEVICE Power Supply Current Standby (Logic Inputs Grounded) Operating (CL = 1.0 nF Drive Outputs 1 and 2, f = 100 kHz) Operating Voltage ICC - - VCC 6.5 6.0 10.5 - 8.0 15 18 V mA CL = 1.0 nF CL = 2.5 nF CL = 1.0 nF CL = 2.5 nF ns tPLH (IN/OUT) tPHL (IN/OUT) tr tf - - - - - - 55 40 14 36 15 32 120 120 30 - 30 - ns ns V VOL - - - 10.5 10.4 10 - 0.8 1.1 1.8 11.2 11.1 10.8 100 1.2 1.5 2.5 - - - - kW VIH VIL IIH IIL - 0.8 - - 1.75 1.58 100 20 2.6 - mA 300 100 V Symbol Min Typ Max Unit VOH RPD 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0C for MC34152, -40C for MC33152, -40C for MC33152V Thigh = +70C for MC34152, +85C for MC33152, +125C for MC33152V NCV33152: Tlow = -40C, Thigh = +125C. Guaranteed by design. http://onsemi.com 3 MC34152, MC33152, NCV33152 12V 4.7 + 6 + - 0.1 + 5.7V Logic Input 50 2 100k 7 Drive Output CL 5V Logic Input tr, tf 10 ns 0V 10% tPLH 10% Drive Output 90% 4 100k 5 tPHL 3 90% tr tf Figure 2. Switching Characteristics Test CIrcuit Figure 3. Switching Waveform Definitions 2.4 Vth , INPUT THRESHOLD VOLTAGE (V) 2.0 Iin , INPUT CURRENT (mA) 1.6 1.2 0.8 0.4 0 0 2.0 4.0 6.0 8.0 Vin, INPUT VOLTAGE (V) 10 12 VCC = 12 V TA = 25C 2.2 VCC = 12 V 2.0 1.8 1.6 1.4 1.2 1.0 -55 -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 100 125 Lower Threshold High State Output Upper Threshold Low State Output Figure 4. Logic Input Current versus Input Voltage tPLH(In/Out) , DRIVE OUTPUT PROPAGATION DELAY (ns) tPHL(In/Out) , DRIVE OUTPUT PROPAGATION DELAY (ns) Figure 5. Logic Input Threshold Voltage versus Temperature 200 160 120 80 40 0 Vth(lower) VCC = 12 V CL = 1.0 nF TA = 25C Overdrive Voltage is with Respect to the Logic Input Lower Threshold 200 160 120 80 40 0 Vth(upper) 0 1 2 3 4 Vin, INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V) Overdrive Voltage is with Respect VCC = 12 V to the Logic Input Upper Threshold CL = 1.0 nF TA = 25C -1.6 -1.2 -0.8 -0.4 0 Vin, INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V) Figure 6. Drive Output High to Low Propagation Delay versus Logic Input Overdrive Voltage Figure 7. Drive Output Low to High Propagation Delay versus Logic Input Overdrive Voltage http://onsemi.com 4 MC34152, MC33152, NCV33152 Vclamp, OUTPUT CLAMP VOLTAGE (V) VCC = 12 V Vin = 0 V to 5.0 V CL = 1.0 nF TA = 25C 3.0 2.0 1.0 0 0 GND -1.0 0 0.2 0.4 0.6 VCC High State Clamp (Drive Output Driven Above VCC) 90% - VCC = 12 V 80 ms Pulsed Load 120 Hz Rate TA = 25C Drive Output 10% - Logic Input 50 ns/DIV Low State Clamp (Drive Output Driven Below Ground) 0.8 1.0 1.2 1.4 IO, OUTPUT CLAMP CURRENT (A) Figure 8. Propagation Delay Figure 9. Drive Output Clamp Voltage versus Clamp Current V sat, OUTPUT SATURATION VOLTAGE (V) V sat, OUTPUT SATURATION VOLTAGE (V) 0 VCC 0 -0.5 -0.7 -0.9 -1.1 1.9 1.7 1.5 1.0 0.8 0.6 0 -55 Source Saturation (Load to Ground) VCC = 12 V VCC Isource = 10 mA Isource = 400 mA -1.0 -2.0 -3.0 3.0 2.0 1.0 0 0 0.2 0.4 Source Saturation VCC = 12 V (Load to Ground) 80 ms Pulsed Load 120 Hz Rate TA = 25C Isink = 400 mA Sink Saturation (Load to VCC) 0.6 0.8 Isink = 10 mA Sink Saturation (Load to VCC) -25 0 GND 25 50 75 100 125 GND 1.0 1.2 1.4 IO, OUTPUT CLAMP CURRENT (A) TA, AMBIENT TEMPERATURE (C) Figure 10. Drive Output Saturation Voltage versus Load Current Figure 11. Drive Output Saturation Voltage versus Temperature 90% - 90% - VCC = 12 V Vin = 0 V to 5.0 V CL = 1.0 nF TA = 25C 10% - VCC = 12 V Vin = 0 V to 5.0 V CL = 1.0 nF TA = 25C 10% - 10 ns/DIV 10 ns/DIV Figure 12. Drive Output Rise Time Figure 13. Drive Output Fall Time http://onsemi.com 5 MC34152, MC33152, NCV33152 t r -t f , OUTPUT RISE-FALL TIME(ns) 80 ICC , SUPPLY CURRENT (mA) VCC = 12 V VIN = 0 V to 5.0 V TA = 25C 80 VCC = 12 V Both Logic Inputs Driven 0 V to 5.0 V 50% Duty Cycle Both Drive Outputs Loaded TA = 25C f = 500 kHz 20 60 60 f = 200 kHz 40 tf tr 0 0.1 1.0 CL, OUTPUT LOAD CAPACITANCE (nF) 10 40 20 f = 50 kHz 0 0.1 1.0 CL, OUTPUT LOAD CAPACITANCE (nF) 10 Figure 14. Drive Output Rise and Fall Time versus Load Capacitance 80 ICC , SUPPLY CURRENT (mA) 1 2 3 4 ICC , SUPPLY CURRENT (mA) Both Logic Inputs Driven 0 V to 5.0 V, 50% Duty Cycle Both Drive Outputs Loaded TA = 25C 1 - VCC = 18 V, CL = 2.5 nF 2 - VCC = 12 V, CL = 2.5 nF 3 - VCC = 18 V, CL = 1.0 nF 4 - VCC = 12 V, CL = 1.0 nF 8.0 Figure 15. Supply Current versus Drive Output Load Capacitance TA = 25C 6.0 Logic Inputs at VCC Low State Drive Outputs 60 40 4.0 Logic Inputs Grounded High State Drive Outputs 2.0 20 0 10 k 100 f, INPUT FREQUENCY (Hz) 1.0 M 0 0 4.0 8.0 12 VCC, SUPPLY VOLTAGE (V) 16 Figure 16. Supply Current versus Input Frequency Figure 17. Supply Current versus Supply Voltage APPLICATIONS INFORMATION Description Output Stage The MC34152 is a dual noninverting high speed driver specifically designed to interface low current digital circuitry with power MOSFETs. This device is constructed with Schottky clamped Bipolar Analog technology which offers a high degree of performance and ruggedness in hostile industrial environments. Input Stage The Logic Inputs have 170 mV of hysteresis with the input threshold centered at 1.67 V. The input thresholds are insensitive to VCC making this device directly compatible with CMOS and LSTTL logic families over its entire operating voltage range. Input hysteresis provides fast output switching that is independent of the input signal transition time, preventing output oscillations as the input thresholds are crossed. The inputs are designed to accept a signal amplitude ranging from ground to VCC. This allows the output of one channel to directly drive the input of a second channel for master-slave operation. Each input has a 30 kW pulldown resistor so that an unconnected open input will cause the associated Drive Output to be in a known low state. Each totem pole Drive Output is capable of sourcing and sinking up to 1.5 A with a typical `on' resistance of 2.4 W at 1.0 A. The low `on' resistance allows high output currents to be attained at a lower VCC than with comparative CMOS drivers. Each output has a 100 kW pulldown resistor to keep the MOSFET gate low when VCC is less than 1.4 V. No over current or thermal protection has been designed into the device, so output shorting to VCC or ground must be avoided. Parasitic inductance in series with the load will cause the driver outputs to ring above VCC during the turn-on transition, and below ground during the turn-off transition. With CMOS drivers, this mode of operation can cause a destructive output latchup condition. The MC34152 is immune to output latchup. The Drive Outputs contain an internal diode to VCC for clamping positive voltage transients. When operating with VCC at 18 V, proper power supply bypassing must be observed to prevent the output ringing from exceeding the maximum 20 V device rating. Negative output transients are clamped by the internal NPN pullup transistor. Since full supply voltage is applied across http://onsemi.com 6 MC34152, MC33152, NCV33152 the NPN pullup during the negative output transient, power dissipation at high frequencies can become excessive. Figures 20, 21, and 22 show a method of using external Schottky diode clamps to reduce driver power dissipation. Undervoltage Lockout An undervoltage lockout with hysteresis prevents erratic system operation at low supply voltages. The UVLO forces the Drive Outputs into a low state as VCC rises from 1.4 V to the 5.8 V upper threshold. The lower UVLO threshold is 5.3 V, yielding about 500 mV of hysteresis. Power Dissipation aid in this calculation, power MOSFET manufacturers provide gate charge information on their data sheets. Figure 18 shows a curve of gate voltage versus gate charge for the ON Semiconductor MTM15N50. Note that there are three distinct slopes to the curve representing different input capacitance values. To completely switch the MOSFET `on,' the gate must be brought to 10 V with respect to the source. The graph shows that a gate charge Qg of 110 nC is required when operating the MOSFET with a drain to source voltage VDS of 400 V. 16 VGS , GATE-TO-SOURCE VOLTAGE (V) MTM15B50 ID = 15 A TA = 25C VDS = 100 V VDS = 400 V Circuit performance and long term reliability are enhanced with reduced die temperature. Die temperature increase is directly related to the power that the integrated circuit must dissipate and the total thermal resistance from the junction to ambient. The formula for calculating the junction temperature with the package in free air is: TJ = TA + PD (RqJA) where: TJ = Junction Temperature TA = Ambient Temperature PD = Power Dissipation RqJA = Thermal Resistance Junction to Ambient 12 8.0 8.9 nF 4.0 2.0 nF 0 D Qg CGS = D V GS 40 80 120 Qg, GATE CHARGE (nC) 160 0 There are three basic components that make up total power to be dissipated when driving a capacitive load with respect to ground. They are: PD = PQ + PC + PT where: PQ = Quiescent Power Dissipation PC = Capacitive Load Power Dissipation PT = Transition Power Dissipation Figure 18. Gate-to-Source Voltage versus Gate charge The capacitive load power dissipation is directly related to the required gate charge, and operating frequency. The capacitive load power dissipation per driver is: PC(MOSFET) = VCC Qg f The quiescent power supply current depends on the supply voltage and duty cycle as shown in Figure 17. The device's quiescent power dissipation is: PQ = VCC (ICCL [1-D] + ICCH [D]) where: ICCL = Supply Current with Low State Drive Outputs ICCH = Supply Current with High State Drive Outputs D = Output Duty Cycle The capacitive load power dissipation is directly related to the load capacitance value, frequency, and Drive Output voltage swing. The capacitive load power dissipation per driver is: PC = VCC (VOH - VOL) CL f where: VOH VOL CL f = = = = High State Drive Output Voltage Low State Drive Output Voltage Load Capacitance Frequency The flat region from 10 nC to 55 nC is caused by the drain-to-gate Miller capacitance, occurring while the MOSFET is in the linear region dissipating substantial amounts of power. The high output current capability of the MC34152 is able to quickly deliver the required gate charge for fast power efficient MOSFET switching. By operating the MC34152 at a higher VCC, additional charge can be provided to bring the gate above 10 V. This will reduce the `on' resistance of the MOSFET at the expense of higher driver dissipation at a given operating frequency. The transition power dissipation is due to extremely short simultaneous conduction of internal circuit nodes when the Drive Outputs change state. The transition power dissipation per driver is approximately: PT VCC (1.08 VCC CL f - 8 x 10-4) PT must be greater than zero. When driving a MOSFET, the calculation of capacitive load power PC is somewhat complicated by the changing gate to source capacitance CGS as the device switches. To Switching time characterization of the MC34152 is performed with fixed capacitive loads. Figure 14 shows that for small capacitance loads, the switching speed is limited by transistor turn-on/off time and the slew rate of the internal nodes. For large capacitance loads, the switching speed is limited by the maximum output current capability of the integrated circuit. http://onsemi.com 7 MC34152, MC33152, NCV33152 LAYOUT CONSIDERATIONS High frequency printed circuit layout techniques are imperative to prevent excessive output ringing and overshoot. Do not attempt to construct the driver circuit on wire-wrap or plug-in prototype boards. When driving large capacitive loads, the printed circuit board must contain a low inductance ground plane to minimize the voltage spikes induced by the high ground ripple currents. All high current loops should be kept as short as possible using heavy copper runs to provide a low impedance high frequency path. For optimum drive VCC 47 0.1 6 + - performance, it is recommended that the initial circuit design contains dual power supply bypass capacitors connected with short leads as close to the VCC pin and ground as the layout will permit. Suggested capacitors are a low inductance 0.1 mF ceramic in parallel with a 4.7 mF tantalum. Additional bypass capacitors may be required depending upon Drive Output loading and circuit layout. Proper printed circuit board layout is extremely critical and cannot be over emphasized. Vin Vin 5.7V 2 TL494 or TL594 4 100k 100k 7 Rg 100k D1 1N5819 5 3 The MC34152 greatly enhances the drive capabilities of common switching regulators and CMOS/TTL logic devices. Series gate resistor Rg may be needed to damp high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate-source circuit. Rg will decrease the MOSFET switching speed. Schottky diode D1 can reduce the driver's power dissipation due to excessive ringing, by preventing the output pin from being driven below ground. Figure 19. Enhanced System Performance with Common Switching Regulators Figure 20. MOSFET Parasitic Oscillations 7 100k 4X 1N5819 5 100k Isolation Boundary 100k 3 Output Schottky diodes are recommended when driving inductive loads at high frequencies. The diodes reduce the driver's power dissipation by preventing the output pins from being driven above VCC and below ground. 1N 5819 3 Figure 21. Direct Transformer Drive Figure 22. Isolated MOSFET Drive http://onsemi.com 8 MC34152, MC33152, NCV33152 IB + Vin 0 - Base Charge Removal C1 Vin Rg(on) 100k Rg(off) In noise sensitive applications, both conducted and radiated EMI can be reduced significantly by controlling the MOSFET's turn-on and turn-off times. The totem-pole outputs can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor C1. Figure 23. Controlled MOSFET Drive VCC = 15V 47 + 0.1 6 + - 5.7V 2 100k 7 Figure 24. Bipolar Transistor Drive + 6.8 10 + 100k 1N5819 + VO 2 .0VCC + 47 5 100k 6.8 10 + 1N5819 47 VCC 10k 2N3904 100k 330 pF 4 - VO -VCC + 3 Output Load Regulation The capacitor's equivalent series resistance limits the Drive Output Current to 1.5 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. IO (mA) 0 1.0 10 20 30 50 +VO (V) 27.7 27.4 26.4 25.5 24.6 22.6 -VO (V) -13.3 -12.9 -11.9 -11.2 -10.5 -9.4 Figure 25. Dual Charge Pump Converter http://onsemi.com 9 MC34152, MC33152, NCV33152 PACKAGE DIMENSIONS PDIP-8 CASE 626-05 ISSUE L 8 5 -B- 1 4 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040 F NOTE 2 -A- L C -T- SEATING PLANE J N D K M M H G 0.13 (0.005) TA M B M http://onsemi.com 10 MC34152, MC33152, NCV33152 PACKAGE DIMENSIONS SOIC-8 D SUFFIX CASE 751-07 ISSUE AC -X- A 8 5 B 1 4 S 0.25 (0.010) M Y M -Y- G C -Z- H D 0.25 (0.010) M SEATING PLANE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 11 MC34152, MC33152, NCV33152 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 12 MC34152/D |
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